The present invention relates to a constant voltage generating circuit for a semiconductor device. More particularly, the present invention relates to a circuit which generates a constant voltage at a level stabilized between two power supply voltages, and which finds application in semiconductor memory devices.
Increased integration of semiconductor memory devices has resulted in unit memory cells of extremely small size. Along with the sharp reduction in physical size, memory cells in highly integrated semiconductor memory devices also require a reduced operating voltage, that is, a reduced supply voltage Vcc. Past requirements for stable semiconductor operating voltages have been meet by well known constant voltage generating circuits. These well known constant voltage generating circuits include; the substrate voltage generating circuit, the reference voltage generating circuit, and the half power supply voltage generating circuit (hereinafter"half Vcc generating circuit"). Of these, the half Vcc generating circuit has found particular application in precharging bit lines and/or data lines in semiconductor memory devices. In fact, the need for stable, efficient half Vcc generating circuits continues to expand with the increased demands of next generation semiconductor memory devices.
This expanding need was originally addressed in U.S. Pat. No. 4,663,584. This patent discloses a half Vcc generating circuit, shown for example in FIG. 1, which is readily implemented in CMOS logic. As can be seen in FIG. 1, the half Vcc generating circuit comprises a bias circuit 40, and driver circuit 50. Bias circuit 40 generates first and second reference voltages in accordance with the voltage difference between power supply voltages Vcc and Vss. Driver circuit 50 generates half power supply voltage (Vm) in accordance with the first and second reference voltages.
Bias circuit 40 comprises p-channel MOS transistor Q5, n-channel MOS transistor Q1, p-channel MOS transistor Q2, and n-channel MOS transistor Q6 which are serially connected between a first power supply voltage Vcc and a second power supply voltage Vss. The gate of Q5 is connected to Vss along with the source of Q6. The source of Q5 is connected to Vcc along with the gate of Q6. The gate and drain of Q1, as well as the drain of Q5 are commonly connected to a first voltage node n1 at which the first reference voltage is apparent. The source of Q2 and the source of Q1 are commonly connected at a third voltage node n3, The gate and drain of Q2, as well as the drain of Q6 are commonly connected to a second voltage node n2 at which the second reference voltage is apparent.
Driver circuit 50 comprises n-channel transistor Q3, and p-channel transistor Q4 serially connected between Vcc and Vss. The gate of Q3 receives the first reference voltage from node n1, and the gate of Q4 receives the second reference voltage from node n2. The drain of Q3 is connected to Vcc, and the drain of Q4 is connected to Vss. Finally, the source of Q3 and the source of Q4 are commonly connected at node n4 at which the half power supply voltage Vm is apparent.
In operation, the voltage at node n1 becomes 1/2 Vcc+V.sub.TQ1, wherein V.sub.TQ1 equals the threshold voltage of Q1, when node n3 is equal to 1/2 Vcc. Similarly, the voltage at node n2 becomes 1/2 Vcc+V.sub.TQ2, wherein V.sub.TQ2 equals the threshold voltage of Q2, when node n3 is equal to 1/2 Vcc. If, under these conditions, Vm is lower than the voltage at node n1, then Q3 is slightly turned ON, thereby increasing the voltage at node n4. On the other hand, if Vm is higher than the voltage at node n2, then Q4 slightly turned ON, thereby decreasing the voltage at node n4. As a result, Vm is precisely adjusted to 1/2 Vcc.
The above described conventional half power supply generating circuit operates very well, until such time as Vm falls below a predetermined level. When Vm falls below this predetermined level, because, for example, of an abrupt current drain brought about by transient loading, Vm is very slow to recover. Slow Vm recovery precludes (or limits) high-speed operation of a semiconductor memory device incorporating the above conventional circuit.
Another conventional half power supply voltage generating circuit which addresses the problem described above is shown in FIG. 2. This second conventional circuit is used by Matsushita in its 4 Mbit dynamic RAM. The bias circuit 41 of the second conventional circuit differs from the bias circuit 40 of the first conventional circuit in the connection of transistors Q5 and Q6. In the circuit shown in FIG. 1, Q5 and Q6 were always ON. However, in the circuit shown in FIG. 2, Q5 and Q6 are controlled by the output of the half power supply voltage Vm apparent at node n4. This feature allows better Vm recovery time and, thus, better start-up and high-speed operation.
The operation of the second conventional circuit will now be described with reference to FIG. 2 and to FIG. 5. The unevenly dotted line in FIG. 5 illustrates the voltage-current characteristic curve for the circuit shown in Fig. 2. In the circuit shown in FIG. 2, as the voltage at node n1 rises above the threshold voltage VTQ3, due to an increase in the level of Vcc, Q3 is turned ON, thereby increasing the voltage at node n4. See, for example, Vcc1 in FIG. 5. As Vcc continues to increase to Vcc2, but the voltage at node n1 remains lower than the sum of the threshold voltages V.sub.TQ1 +V.sub.TQ2, the bias circuit 41 does not "set up." Under these circumstances, if Vm is greater than V.sub.TQ6, then Q6 is turned ON and node n2 goes to Vss, thereby also turning Q4 ON.
In other words, transistors Q3 and Q4 are both turned ON for some time period preceding the "set up" of the bias circuit 41. This creates direct current path between Vcc and Vss in the driver circuit. This also results in node n1 having a voltage level equal to Vcc and node n2 having a voltage level equal to Vss. The resulting current flow is shown by the evenly dotted line in FIG. 5.
As Vcc is increased upward through Vcc3 to Vcc4, transistors Q1 and Q2 are operated in a diode fashion within the bias circuit 41 to adjust the voltages at nodes n1 and n2. The voltage at node n2 moves from Vss to a DC level determined by the channel resistances of Q5, Q1, Q2, and Q6. Meanwhile, the voltage at node n1 also assumes a DC level between Vcc and Vss. These voltage node adjustments cause the gate-source voltages of Q4 and Q3 (V.sub.GSQ4, V.sub.GSQ3) to decrease, thereby reducing current flow between Q3 and Q4. Since current flows through the bias circuit 41, the current in the driver section 51 is reduced. This result is shown in FIG. 5 between power supply voltage of Vcc3 and Vcc4.
Finally, as Vcc is increased to completely set up the bias circuit 41, node n1 moves to 1/2 Vcc+V.sub.TQ1, and node n2 moves to 1/2 Vcc-V.sub.TQ2, such that Q3 and Q4 are slightly turned ON. In response, current flow through Q3 and Q4 is drastically reduced, and direct current flows through the bias circuit 41. See FIG. 5 for Vcc exceeding Vcc4.
Unfortunately, while addressing the Vm recovery problem associated with the first conventional half Vcc generating circuit, the second conventional circuit shown in FIG. 2 suffers from several other problems. Among these problems is excessive power consumption. This is primarily the result of the "short-circuit" current flow in the driver section 51 during the rise of Vcc from Vcc2 to Vcc4 in FIG. 5. Excessive power consumption is particularly prevalent for low Vcc voltage levels. Additionally, since Vcc and Vss are directly connected to the drains of Q3 and Q4 respectively, it is difficult to protect the conventional half Vcc generating circuit from electrostatic discharge.